Search - 8051 IP

[VHDL-FPGA-Verilog] mc8051-VHDL

Description: VHDL实现 8051 CPU核 Oregano Systems 8-bit Microcontroller IP-Core-VHDL 8051 CPU nuclear Oregano Systems 8-bit Mic rocontroller IP-Core
Platform: | Size: 614400 | Author: 陈同 | Hits:

[VHDL-FPGA-Verilog] 8051-vhdl-code

Description:
Platform: | Size: 98304 | Author: 周华茂 | Hits:

[TCP/IP stack] zlIP-8051-rtl8019as

Description: 大侠编写的国产tcp/ip协议栈, 绝对超值！-Heroes prepared homemade tcp/ip protocol stack, the absolute value!
Platform: | Size: 300032 | Author: 晕来晕去 | Hits:

[SCM] Embedded.-.Ethernet.8051.Tcp.Ip.Keil.Control.Inter

Description: tiny tcpip on 8051 可以利用在單片機各種相關應用-tiny tcpip on 8051 can use a variety of related applications in SCM
Platform: | Size: 456704 | Author: maverick | Hits:

[SCM] 8051ipcore

Description: 8051的IP内核，用verilog编写，可以实现8051的一般功能-8051 IP core, prepared using Verilog, you can realize the general function of 8051
Platform: | Size: 52224 | Author: 王天 | Hits:

[VHDL-FPGA-Verilog] mc8051_design

Description: This is version 1.4 of the MC8051 IP core.
Platform: | Size: 782336 | Author: 俞宏锦 | Hits:

[VHDL-FPGA-Verilog] mc8051

Description: 可在FPGA上运行的8051 IP core,是学习FPGA及SPOC的好资料。-FPGA can be run on 8051 IP core, is to learn from FPGA and SPOC good information.
Platform: | Size: 394240 | Author: ygl | Hits:

[Software Engineering] 8051-GPS

Description: 介绍了基于GPRS网的数据传输、嵌入式实时操作系统u/OS-II以及小型TCP/IP协议栈uIP；深入论述了基于8051嵌入式系统的GPRS终端的实现。提供了一种罗为简单、廉价和实用的GPRS终端的实现方案，说明了在8051中如何进行uC/OS-II和uIP的移植。-Introduction based on the GPRS network, data transmission, embedded real-time operating system u/OS-II and small TCP/IP protocol stack uIP go into the 8051-based embedded systems realize GPRS terminals. Romania provides a simple, cheap and practical realization of the GPRS terminal program, described in 8051 how to uC/OS-II and uIP transplant.
Platform: | Size: 83968 | Author: yangdaicheng | Hits:

[Program doc] DMX512

Description: DMX512协议最先是由USITT（美国剧院技术协会）发展成为从控制台用标准数字接口控制调光器的方式，但是传统上的信号传输依赖于485接口方式的双绞线，在使用灵活上大打折扣！而基于TCP/IP的无线传输由于时延大，控制数据实时性差等，也很难满足需求-DMX512 protocol is the first USITT (United States Association of Theater Technology) to develop into from the console using a standard digital interface control dimmers way, but traditionally dependent on the signal transmission means 485 of the twisted pair, the reduced flexibility in the use of ! And based on TCP/IP wireless transmission delay due to large, poor real-time control data, it is difficult to meet demand
Platform: | Size: 908288 | Author: eastward | Hits:

[VHDL-FPGA-Verilog] 8051IP

Description: 8051的IP,采用VHDL语言描述,支持intel的HEX格式,包括中断,定时器等.-8051 IP, the use of VHDL language description, support intel s HEX format, including the interruption, such as timers.
Platform: | Size: 1021952 | Author: 陈 | Hits:

[SCM] 8051_IP_Verilog

Description: 8051单片机源码verilog版本包括rtl， testbench， synthesis -Verilog source code version of 8051, including rtl, testbench, synthesis
Platform: | Size: 508928 | Author: carol | Hits:

[VHDL-FPGA-Verilog] 8051

Description: alter公司的mcu核，8051ip核，为quartus2设计，其他应该兼容 -alter the company' s mcu nuclear, 8051ip nuclear, for quartus2 design should be compatible with other
Platform: | Size: 9170944 | Author: cvdsf | Hits:

[VHDL-FPGA-Verilog] mc8051

Description: Oregano Systems 8051 ip核-Oregano Systems 8051 ip core
Platform: | Size: 394240 | Author: horven | Hits:

[VHDL-FPGA-Verilog] C8051_mega_core.tar

Description: 8051单片机软核，测试代码和仿真环境，可直接上fpga使用，是一个成熟的ip核。经本人仿真以及在fpga上测试，完全正常。-8051 soft ip core, testbench, simulation environment
Platform: | Size: 719872 | Author: sdwsh | Hits:

[VHDL-FPGA-Verilog] 8051code

Description: VHDL源码 8051+IP内核在xilinx环境仿真运行不带接口的逻辑部分代码-VHDL source code 8051+ IP cores in the xilinx environment simulation to run without a logical part of the code interface
Platform: | Size: 98304 | Author: 王力 | Hits:

[VHDL-FPGA-Verilog] DDR

Description: HYB25025616的IP核，可直接用于microblaze的应用里，在合众达FEM024板子直接使用-HYB25025616 the IP core, can be used directly microblaze application, the board in the Triangle over FEM024 directly
Platform: | Size: 3968000 | Author: 网络蚂蚁 | Hits:

[VHDL-FPGA-Verilog] 8051

Description: 51ip核用vhdl编写在迅雷上下载-51 ip core write with vhdl
Platform: | Size: 5813248 | Author: shenyf | Hits:

[VHDL-FPGA-Verilog] 8051vlog

Description: 8051IP核，verilog源代码，包含测试向量，-8051 IP Core verilog code， with testbench
Platform: | Size: 251904 | Author: zhangq | Hits:

[VHDL-FPGA-Verilog] mc8051-IP

Description: VHDL 8051 IP, VHDL写的8051的IP核。-VHDL 8051 IP
Platform: | Size: 394240 | Author: Bob | Hits:

[VHDL-FPGA-Verilog] 8051-IP

Description: The synchronous 8051 microcontroller is a common processor found in many embedded systems. By using asynchronous design techniques, the performance of the 8051 microcontroller is increased. Through simulation and the use of existing synchronous design tools in the asynchronous design flow, a four-phase handshaking approach with a stoppable clock is simulated and then implemented. The asynchronous architecture added to the existing synchronous architecture includes an ALU wrapper, a controller wrapper, and a clocking element. The asynchronous design flow consists of functional simulation, synthesis of synchronous blocks, timing analysis, asynchronous wrapper design, and timing simulation. After implementation analysis, the asynchronous 8051 is 28.7 faster then the synchronous 8051 while only using 10 more area.-The synchronous 8051 microcontroller is a common processor found in many embedded systems. By using asynchronous design techniques, the performance of the 8051 microcontroller is increased. Through simulation and the use of existing synchronous design tools in the asynchronous design flow, a four-phase handshaking approach with a stoppable clock is simulated and then implemented. The asynchronous architecture added to the existing synchronous architecture includes an ALU wrapper, a controller wrapper, and a clocking element. The asynchronous design flow consists of functional simulation, synthesis of synchronous blocks, timing analysis, asynchronous wrapper design, and timing simulation. After implementation analysis, the asynchronous 8051 is 28.7 faster then the synchronous 8051 while only using 10 more area.
Platform: | Size: 245760 | Author: Sanju464 | Hits:

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[VHDL-FPGA-Verilog] mc8051-VHDL

[VHDL-FPGA-Verilog] 8051-vhdl-code

[TCP/IP stack] zlIP-8051-rtl8019as

[SCM] Embedded.-.Ethernet.8051.Tcp.Ip.Keil.Control.Inter

[SCM] 8051ipcore

[VHDL-FPGA-Verilog] mc8051_design

[VHDL-FPGA-Verilog] mc8051

[Software Engineering] 8051-GPS

[Program doc] DMX512

[VHDL-FPGA-Verilog] 8051IP

[SCM] 8051_IP_Verilog

[VHDL-FPGA-Verilog] 8051

[VHDL-FPGA-Verilog] mc8051

[VHDL-FPGA-Verilog] C8051_mega_core.tar

[VHDL-FPGA-Verilog] 8051code

[VHDL-FPGA-Verilog] DDR

[VHDL-FPGA-Verilog] 8051

[VHDL-FPGA-Verilog] 8051vlog

[VHDL-FPGA-Verilog] mc8051-IP

[VHDL-FPGA-Verilog] 8051-IP

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